1. Field of the Invention
The present invention relates to manipulation of output signals from memory devices and, in particular, concerns a circuit for latching data signals output from a DRAM memory device so that a memory controller can better access the data signals.
2. Description of the Related Art
Memory devices are used in all types of processing circuits. DRAM and SRAM memories are two typical memory devices that are commonly used in computer applications. Generally, data is stored in these types of memories in an array of cells wherein the array of cells is addressable by row and column. Typically, when a memory processor, such as a memory controller, wishes to access data within the memory, a row address and column address signal is sent to the memory and, after a short period of time, the data contained within the appropriate cells is output on a data bus.
One difficulty with memory circuits is that the processor needs to be able to access the data in memory very quickly. For the standard DRAM circuit, the access time can be so long that the processor has to sit idle awaiting the data from the memory, thereby slowing down the system incorporating the processor. The standard DRAM access cycle is comprised of the steps of 1) placing the row address of the storage cells to be accessed on the address input pins of the memory chip, 2) placing a logic low signal on the row address select (RAS) input pin, 3) placing the column address of the storage cells to be accessed on the address input pins of the memory chip, and 4) placing a logic low on the column address select (CAS) input pin. After this cycle has been completed, which usually takes 60-80 nanoseconds, the data is output from the memory device typically after a delay of 15 to 20 nanoseconds. It will be appreciated that computer circuits have to repeatedly perform this access cycle during normal operation. Hence, performing each of these steps for each piece of data which the processor requires can result in the processor operating at a slow rate.
To address this problem in the particular applications of DRAM memories, DRAMs incorporating other access cycles have been developed. For example, one typical access cycle is known as the fast page mode (FPM) access cycle. The FPM access cycle is similar to the standard access cycle described above except the memory is organized so that a "page" corresponds to one row of addresses. Hence, in the FPM memory once the processor accesses data the first time from a page, on each subsequent cycle where the processor is accessing data from the same page, the RAS input remains low and the previously entered row address signals are maintained. For each subsequent cycle of an FPM DRAM memory, where the processor is seeking data that is contained on the same page as the previously sought data, the processor simply has to place the new column address signals on the address input pins and then place a logic low on the CAS pin to obtain the data. Hence, in the FPM DRAM device, the steps of placing the row address inputs on the address input pins and placing a low RAS signal on the RAS input pin are only required when data is being sought on a different page and can otherwise be eliminated. This results in faster access of data by the processor.
FIG. 1A is a timing diagram which illustrates a series of typical data cycles of an FPM DRAM memory wherein data stored on the same page is being accessed. As shown in FIG. 1A, the data is valid, i.e., accessible to the processor requesting the data, from a short time after the CAS period has gone low to a short time after the CAS signal goes high again. The access time for each cycle in an FPM DRAM device is defined as the time period from where the CAS signal goes high to the time at which the next valid data signals are output on the data output pins. One can appreciate, in viewing FIG. 1A, that the time period where the data is valid is substantially less than the access time for the processor to obtain data out of an FPM mode DRAM device successively reading data off of the same page in memory.
The fact that the data is valid for such a short period of time in the FPM DRAM memory requires that the processor be scheduled to read the data during this short time interval. Hence, in situations where the processor is receiving data from more than one memory device, scheduling for the processor to access the data from any one FPM memory is complicated by the limited period of time that the data is valid on the data output pins. Further, the processor quite often has to idly wait for the data to become valid before proceeding to initiate another data access cycle. For these reasons, the FPM DRAM memories often result in the processor's having to sit idle awating the data thereby causing the processor to be ineffecient. Hence, there was a need for some way of allowing for greater flexibility in scheduling the processor to access data from one or more memory devices to thereby speed up the processor in accessing data from multiple memory devices.
To address this particular need, extended data out (EDO) DRAM memories were developed. An EDO memory is simply an enhancement of the previously existing FPM memory except that the EDO memory latches the data on the output pins during the period of time after the CAS signal goes high until the CAS signal goes low again. This period of time is typically referred to as the CAS precharge time. FIG. 1B illustrates a typical EDO mode access cycle. In the EDO device, a low CAS signal causes the data to be retrieved from the memory. Once the data becomes valid, it stays valid until the CAS signal begins to go low for a subsequent read cycle. Hence, in the EDO device, the data is valid on the output pins for a time period which includes the CAS precharge time. Hence, the memory controller or some other processor can access the data on the output pins of the EDO memory for a longer period of time. This results in easier scheduling of the memory controller and, where the memory controller is being used with more than one memory module, the memory controller is, in fact, faster due to this easier scheduling.
However, one difficulty associated with the EDO devices is that these devices are expensive and are not readily available to users of the chips. In particular, the standard EDO DRAM memory has additional circuitry, including latches and the like, built onto the chip to ensure that the data is maintained during the CAS precharge time. It will be appreciated that this additional circuitry increases the cost of the DRAM memory. Further, since computer manufacturers have begun to use EDO DRAM memory in their computer circuits, the demand for EDO memories has outstripped the supply.
Hence, there is a need in the prior art for an inexpensive memory circuit which can be used with non-EDO memory that will latch data for an extended period of time. In particular, there is a need for an inexpensive circuit which can be used in conjunction with more commonly available DRAM memories, such as FPM mode DRAM memories, that will latch data on the output for an extended period of time.